The present disclosure relates generally to semiconductor structures, and more specifically, relates to semiconductor devices, including 3D vertical gate (VG) NAND devices, and methods of fabricating semiconductor devices, including 3D vertical gate (VG) NAND devices.
There is an ever growing need by semiconductor device manufacturers to further shrink the critical dimensions of semiconductor devices, to achieve greater storage capacity in smaller areas, and to do so at lower cost per bit. Three-dimensional (3D) semiconductor devices using, for example, thin film transistor (TFT) techniques, charge trapping memory techniques, and cross-point array techniques, have been increasingly applied to achieve the above needs by semiconductor manufacturers. Recent developments in semiconductor technology include the forming of vertical NAND cells using charge-trapping memory technology, in which a multi-gate field effect transistor structure having a vertical channel operating like a NAND gate uses silicon-oxide-nitride-oxide-silicon (SONOS) charge trapping technology to create a storage site at each gate/vertical channel interface. Recent developments have achieved reduced critical dimensions, greater storage, and reduced associated manufacturing costs for three-dimensional semiconductor devices by forming stacks of strips of alternating conductive material separated by insulating material and providing memory elements in interface regions between conductive materials of the stacks.